Dave Anderson on Nostr: For a 50MHz eZ80... I don't know what its bus discipline looks like, that's key. From ...

For a 50MHz eZ80... I don't know what its bus discipline looks like, that's key. From the edge that tells the FPGA it can latch an address and do a read, how long does it have to get the right signals on the data bus? And, are the bus and FPGA clocks synchronized? Synchronized clocks can avoid the 2-cycle synchronization delay, which is a pretty huge chunk of the total budget in this case.