Sorry, I just took one of your two arguments away.
1. The source code Verilog/VHDL/SystemC is as a work sufficiently similar to software to be copyrightable.
The other I took away before:
2. The transformation process is similar to compiling software (and I know how to write compilers and synthesis tools) that if one of these transformation processes is agreed to retain copyright, the other must be, too.
The limitations here means I must take one argument at a time.
Bernd Paysan R.I.P Natenom 🕯️ /
npub1jr…n7fcl
2024-07-29 14:09:46
in reply to nevent1q…julh
Author Public Key
npub1jre64lckn3ftn5mp3mmwecj7ysk3mny8k3cxwwe6rlskauvc5dqszn7fclPublished at
2024-07-29 14:09:46Event JSON
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