Dave Anderson on Nostr: Note synchronized clocks don't have to run at the same rate. One just has to be a ...

Note synchronized clocks don't have to run at the same rate. One just has to be a divided version of the other. So you can have a 100MHz FPGA talking to a 50MHz CPU, as long as the two clocks stay in phase such that a rising edge from the CPU corresponds to a rising edge of the FPGA clock. That allows the FPGA to latch inputs without having to worry about metastability, because it's doing so within the window where the CPU guarantees stable/valid values.